18 Emitter-CoupledLogic (Eel) Technology. MOS SRAM Architectures MOS SRAM Cell and Peripheral Circuit Operation Bipolar SRAM Technologies. 10 Static Random Access Memories (SRAMs) 12 SRAM (NMOS and CMOS) Cell Structures. Semiconductor memories: technology, testing, and reliability / Ashok K. Library of Congress Cataloging-in-Publication Data Sharma, Ashok K. For general information on our other products and services please contact our Customer Care Department within the U.S. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, recording, scanning, or otherwise, except as permitted under Section 107 or 108 of the 1976 United States Copyright Act, without either the prior written permission of the Publisher, or authorization through payment of the appropriate per-copy fee to the Copyright Clearance Center, Inc., 222 Rosewood Drive, Danvers, MA 01923, 97, fax 97, or on the web at Requests to the Publisher for permission should be addressed to the Permissions Department,John Wiley & Sons, Inc., 111 River Street, Hoboken, NJ 07030, (201) 748-6011, fax (201) 748-6008, e-mail. 3 Park Avenue, 17th Floor, New York, NY 10016-5997 Published by John Wiley & Sons, Inc., Hoboken, New Jersey. © 1997 THE INSTITUTEOF ELECTRICAL AND ELECTRONICS ENGINEERS, INC. ~INTERSCIENCE A JOHNWILEY & SONS, INC.,PUBLICATION The Institute of Electrical and Electronics Engineers, Inc., New York IEEE Solid-State Circuits Council, Sponsor Technical Reviewers Shri Agarwal Jet Propulsion Laboratoriesĭavid Hoff Cypress Semiconductor Jim Kinnison Johns Hopkins University Rob Penchuk IEEE Solid-StateCircuits Council, Sponsor SSc-c Liaison to IEEE Press Stu Tewksbury West Virginia University Kay, Director of Book Publishing John Griffin, Senior Editor Lisa Dayne, Assistant Editor Linda Matarazzo, Editorial Assistant Orlando Velez, Production Editor
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